1. Field of the Invention
The present invention relates generally to electronic circuits, and in particular, to phase shift and duty cycle correction in clock generation circuits.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many electronic systems include one or more synchronous components that rely on receiving related signals at substantially the same time to maintain proper operating characteristics of the electronic system. A computer system is one example of a synchronous system that may include a multitude of interrelated system components, each designed to perform a particular operation in response to a clock signal. In some cases, data transfer between system components may be synchronized by one or more clock signals originating from a common source. The system components may receive the clock signals through a clocking network, which may include clock generation and distribution circuits.
In some cases, clock generation may be accomplished by manipulating the output of a source, such as a crystal oscillator, to generate a plurality of clock signals in accordance with the needs of various components within the computer system. The generated clock signals may be fanned out to the system components via a clock distribution network. In an ideal situation, the generated clock signals may be received by each of the system components at substantially the same time. In practice, however, timing delays and uncertainties of clock signal generation and distribution may cause one or more system components to receive clock signals at slightly different instances. In some cases, even the smallest variation in the arrival of a clock signal transition relative to a data signal transition may significantly impact system performance and/or reliability. For this reason, good clock distribution tends to be very important in the overall performance and reliability of electronic systems. Unwanted clock skew and jitter are two phenomena that may result from poor clock distribution, thus causing problems in the design and operation of the electronic systems.
As used herein, the term “skew” may be described as a variation in the arrival times of two related signals, which are specified to arrive at the same time. For example, “clock skew” may occur when an active “transition” or “edge” of the clock signal “lags” (i.e., arrives sometime after) or “leads” (i.e., arrives sometime before) the data signal transition(s) received by a system component. Clock skew may be introduced into a clocking network through load mismatches, routing parasitics (i.e., interlayer dielectric thickness, interconnect thickness and channel length mismatches), and/or variations in temperature, voltage, and process (i.e., trace conductor length, width, and composition mismatches, capacitive loading, etc.).
Unfortunately, clock skew may adversely affect the timing margins of one or more components within a synchronous system. For example, it is often necessary to properly align the clock signal to the data being sampled at the input latches of a system component to achieve synchronous operation. Such alignment may ensure that the data transition occurs at the proper moment between the edges or active transitions of the clock signal. Synchronous systems, therefore, generally rely on data transitioning and remaining stable from a time, which occurs at least a “setup time” before the clock transition, until at least a “hold time” after the clock transition. Most synchronous system components have stringent setup and hold timing requirements, which are typically specified by a manufacturer of the system component.
As operating speeds increase, the setup and hold timing margins between active transitions of the clock and data signals are reduced, thereby decreasing the window within which a data transition can be successfully latched by a clock transition. For example, edge-sensitive flip-flops may be used for sampling data signals received by a system component. In such an example, a flip-flop may successfully latch a data signal if the data signal is stable during the critical setup and hold periods on either side of the clock transition. However, if clock skew occurs, it may shift the clock transition sufficiently in time to cause a bit error when the data is sampled. As described herein, a “bit error” is a sampling error that occurs when a data signal is incorrectly sampled by a clock transition.
Jitter, on the other hand, generally results from time-varying components of noise sources, and is often defined as the cycle-to-cycle variation in the threshold crossings of a data signal. In other words, jitter may occur in data samples taken near, but not exactly at, the desired sample locations of an individual data signal, such that a sample is temporally displaced by an unknown, though usually small interval (e.g., an interval substantially less than or equal to one clock cycle). Unfortunately, jitter may cause the data signal to be shifted sufficiently in time to produce a bit error when the data signal is incorrectly sampled by the clock signal.
Techniques have been developed to minimize the effects of timing delays, such as clock skew and jitter, which degrade the performance and reliability of synchronous systems. However, most currently used techniques cannot guarantee that a data signal transition will occur at the critical moment between clock signal edges in all conditions. For example, some techniques utilize phase locked loops (PLLs) or delay-locked loops (DLLs) for adding a somewhat variable, though highly consistent amount of delay to a clock path. The added delay may be used to adjust the active edge of a clock signal before it is used for sampling a data signal. As such, a PLL or DLL device could be used to reduce clock skew by adjusting the timing of the clock signal, so that it occurs within the data setup and hold time requirements of a system component. However, the timing delays generated by typical PLL and DLL devices may fail to overcome clock skew in some applications.
Generally speaking, PLLs are closed-loop devices that utilize voltage-controlled oscillators (VCOs) for obtaining accurate phase and frequency alignment between two signals, typically referred to as feedback and reference signals. Though similar, a DLL device generally differs from a PLL device in that it uses a delay line, instead of a VCO, for obtaining accurate phase and frequency alignment between the feedback and reference signals. The VCO of a PLL and the delay line of a DLL may each be used for generating one or more phases, depending on the number of stages included within the VCO or delay line. In some cases, a particular phase may be selected for shifting a transition of a clock signal relative to a data signal transition. In this manner, a PLL or DLL may be used within a phase shift apparatus to provide a somewhat variable, although highly consistent, amount of phase delay by which to shift a clock signal transition.
Conventional phase shift apparatuses often include circuitry for selecting one of the phases output from a PLL or DLL device, or in other words, for “phase picking” from a multi-phase voltage controlled oscillator (VCO) or delay line (DL). A conventional delay locked loop (DLL) is shown in FIG. 1. As illustrated, DLL 100 includes phase frequency detector (PFD) 110, charge pump (CP) 120, loop filter 130 and multi-phase delay line 140. In operation, PFD 110 may compare the phase of the feedback signal (φOUT) to the phase of the reference signal (φREF) and generate corrective “up” and “down” pulses in response thereto. Next, charge pump 120 may compare the durations of the corrective “up” and “down” pulses and generate a net voltage value (VUP/DN), representing an error signal or phase correction signal. Loop filter 130 may then filter the error signal and adjust the delay of multi-phase delay line 140 by supplying a differential control input (Vcon+/−) thereto. When supplied to delay line 140, the differential control input may be used to produce a plurality of phase increments (e.g., φ1, . . . φ5), depending on the number of stages included within the multi-phase delay line.
Though five phase increments are shown in FIG. 1, additional phase increments may be provided by increasing the number of stages within the delay line (e.g., a DLL circuit described in the IEEE Journal of Solid State Circuits, vol. 29, p. 67, January 1994 illustrates a delay line with 128 stages). To facilitate “phase picking”, a first multiplexor 150 may be included within DLL 100 for selecting one of the phases (e.g., φ1, . . . φ5) to be output from the DLL (φOUT) and sent back to the PFD as feedback signal (φFB). In some cases, phase selection from multiplexor 150 may be controlled via a second multiplexor 160 and/or an external selection signal (SEL). The external selection signal may be obtained from an external circuit (not shown) configured for selecting an appropriate clock phase.
The incremental phase delay, or phase resolution, provided by PLL and DLL devices is inversely proportional to the number of stages, N, included within the oscillator or delay line. Unfortunately, the number of stages allowed within an oscillator or delay line is usually limited by the maximum operating frequency, FMAX, of the PLL or DLL. For example, the phase resolution of a PLL or DLL may be approximately equal to 1/(2*FMAX*N), or the minimum delay of one stage, which in current technology may range between about 50–150 picoseconds. As mentioned above, however, the window within which a data transition can be successfully latched by a clock transition decreases as the operating speeds of synchronous systems increase. Therefore, PLL and DLL devices may not provide sufficient phase resolution for accurately controlling timing delays within high-speed synchronous systems. For example, the number of phases output from a PLL or DLL may be limited to about 3–5 as frequency levels increase, thereby limiting the output phase resolution to about ⅓ to ⅕ of the clock period.
In addition to insufficient phase resolution (i.e., large phase increments), PLL/DLL-based phase shift apparatuses generally suffer from limited frequency range and loop stability issues. As a further disadvantage, phase shift apparatuses employing PLLs or DLLs often fail to provide a means for correcting or modifying the duty cycle of the generated output signal. It would, therefore, be desirable to provide an improved phase shift and duty cycle correction circuit and method that does not suffer from the disadvantages of the conventional solution.